`timescale 1ns / 1ps
`include "ExceptStruct.vh"
module MEMWB (
  input         clk,
  input         rst,
  input         stall,
  input         flush,
  input  [63:0] MEM_alu_res,
  input  [63:0] MEM_pc_4,
  input  [63:0] MEM_mem,
  input         MEM_we_reg,
  input  [1:0]  MEM_wb_sel,
  input         MEM_valid,
  input  [31:0] MEM_inst,
  input  [63:0] MEM_pc,
  input  [63:0] MEM_data1,
  input  [63:0] MEM_data2,
  input         MEM_re_mem,
  input  ExceptStruct::ExceptPack MEM_except,
  input         MEM_csr_we,
  input  [63:0] MEM_csr_res,
  input  [63:0] MEM_csr_val,

  output reg [63:0] WB_alu_res,
  output reg [63:0] WB_pc_4,
  output reg [63:0] WB_mem,
  output reg        WB_we_reg,
  output reg [1:0]  WB_wb_sel,
  output reg        WB_valid,
  output reg [31:0] WB_inst,
  output reg [63:0] WB_pc,
  output reg [63:0] WB_data1,
  output reg [63:0] WB_data2,
  output reg        WB_re_mem,
  output ExceptStruct::ExceptPack WB_except,
  output reg        WB_csr_we,
  output reg [63:0] WB_csr_res,
  output reg [63:0] WB_csr_val
);
import ExceptStruct::ExceptPack;

always @(posedge clk) begin
  if (rst | flush) begin
    WB_valid <= 1'b0;
    WB_alu_res <= 64'b0;
    WB_pc_4 <= 64'b0;
    WB_mem <= 64'b0;
    WB_we_reg <= 1'b0;
    WB_wb_sel <= 0;
    WB_inst <= 0;
    WB_pc <= 0;
    WB_data1 <= 0;
    WB_data2 <= 0;
    WB_re_mem <= 0;
    WB_csr_we <= 0;
    WB_csr_res <= 0;
    WB_csr_val <= 0;

    WB_except.ecause <= 0;
    WB_except.epc <= 0;
    WB_except.etval <= 0;
    WB_except.except <= 0;
  end
  else if (~stall) begin
    WB_alu_res <= MEM_alu_res;
    WB_pc_4 <= MEM_pc_4;
    WB_mem <= MEM_mem;
    WB_we_reg <= MEM_we_reg;
    WB_wb_sel <= MEM_wb_sel;
    WB_valid <= MEM_valid;
    WB_inst <= MEM_inst;
    WB_pc <= MEM_pc;
    WB_data1 <= MEM_data1;
    WB_data2 <= MEM_data2;
    WB_re_mem <= MEM_re_mem;
    WB_csr_we <= MEM_csr_we;
    WB_except <= MEM_except;
    WB_csr_res <= MEM_csr_res;
    WB_csr_val <= MEM_csr_val;
  end
end



endmodule